für RFIC Hersteller

RFIC Design Verification

  • analog mixed-signal pre-silicon verification
  • behavioral modeling of analog custom flow design down to “one level above transistor”
  • add phase noise to oscillators and other noise generating blocks’ HDL representation
  • HDL vs. extracted layout testbenches
  • integration into digital flow top-level testbench
  • large experience in QuestaSim® ADMS simulation
  • PLL setup in Accelera® System-C AMS under development
  • 9ys. experience in VHDL modeling and design of cellular transceivers